Embodiments of the present disclosure relate to semiconductor devices and methods of manufacturing the same and, more particularly, to semiconductor devices including spacers on sidewalls of conductive lines and methods of manufacturing the same.
Dynamic random access memory (DRAM) semiconductor devices may include a plurality of memory cells, and each of the memory cells may include a single cell transistor and a single cell capacitor. The cell capacitor may be electrically connected to a storage node contact plug formed between bit lines, and the storage node contact plug may be electrically connected to a semiconductor substrate. When the alignment between the storage node contact plugs and the bit lines is out of an allowed range during a photolithography process for forming the storage node contact plugs, the storage node contact plugs may contact the bit lines.
The semiconductor devices, for example the DRAM devices, may include sense amplifiers electrically connected to the bit lines. As the semiconductor devices have become more highly integrated, a ratio of a capacitance Cs of the cell capacitor to a parasitic capacitance Cb of the bit line has been reduced. Thus, a sensing margin of the sense amplifiers is reduced and may cause malfunction of the semiconductor devices. Accordingly, minimization of the parasitic capacitance between the bit lines and the storage node contact plugs is increasingly desired with the development of highly-integrated, smaller and faster semiconductor memory devices. In particular, as the semiconductor devices are scaled down to a minimum feature size of about several nanometers, the parasitic capacitance between the bit lines and the storage node contact plugs becomes an important parameter affecting operation and/or performance of the semiconductor devices.
In an attempt to reduce the bit line capacitance Cb, techniques for forming a low-k dielectric layer on sidewalls of the bit lines have been proposed. For example, a nitride/oxide/nitride (NON) spacer layer may be formed by depositing a nitride layer on a substrate including conductive lines, oxidizing the nitride layer to form an oxide layer having a lower dielectric constant than the nitride layer at a surface of the nitride layer, and depositing another nitride layer on the oxide layer.
FIG. 1 is a cross sectional view illustrating an exemplary DRAM device including bit line spacers having an NON structure. In FIG. 1, some elements such as landing contact plugs are not shown for the purpose of ease and convenience in explanation.
Referring to FIG. 1, bit line stacks 110 are disposed on a semiconductor substrate 100. Each of the bit line stacks 110 includes a conductive pattern 102 and a hard mask pattern 104 which are sequentially stacked. A storage node contact plug 120 may be disposed between the bit line stacks 110. NON structural spacers 130 (also referred to as NON spacers) are disposed on respective ones of sidewalls of the bit line stacks 110. The NON spacers 130 are disposed to electrically insulate the storage node contact plug 120 from the bit line stacks 110. Each of the NON spacers 130 includes an inner nitride layer (132) contacting the bit line stack 110, an oxide layer (134) on the inner nitride layer (132) opposite to the bit line stack 110, and an outer nitride layer (136) on the oxide layer (134) opposite to the oxide layer (134).
As illustrated in FIG. 1, if an alignment between a storage node electrode hole 160a and the storage node contact plug 120 (or the bit line stacks 110) is outside of an allowed range during a photolithography process for forming the storage node electrode hole 160a that penetrates a sacrificial layer 150 and an etch stop layer 140 to expose the storage node contact plug 120, at least a portion of the NON spacer 130 may be exposed. Further, when the exposed portion of the NON spacer 130 is over-etched, the oxide layer 134 of the exposed NON spacer 130 may be etched faster than the nitride layers 132 and 136 of the exposed NON spacer 130 because an etch rate of the oxide layer 134 is greater than that of the nitride layers 132 and 136. Accordingly, the probability of the electrical shortage between the storage node contact plug 120 and the conductive pattern 102 of the bit line stack 110 may be increased due to a storage node electrode 160 formed in the storage node electrode hole 160a. 